1. Field of the Invention
The present invention relates to a method of determining a defect-free semiconductor integrated circuit such as complementary metal oxide semiconductor (CMOS) integrated circuit.
2. Description of the Related Art
Many of semiconductor integrated circuits (ICs;) are simultaneously formed on a semiconductor wafer by a same design rule, and in same production conditions. However, all of the ICs are always defect-free, and the inspection for the ICs is required. Many inspection methods have been proposed.
Japanese Unexamined Patent Publication (Kokai) No. 8-271584, Japanese Unexamined Patent Publication (Kokai) No. 9-211088, U.S. Pat. Nos. 5,392,293, 5,519,333, and 5,889,408 describe a quiescent power supply current (QPSC, IDDQ) of a CMOS integrated circuit which is a test using an IDDQ In an IDDQ test, the measurement of the quiescent power supply current of a CMOS integrated circuit (IC) is carried out and the determination of defective or indefectible (defect-free) CMOS integrated circuit is carried out based on the measured value. Note that the CMOS integrated circuit to be tested is also called a “IC device under test” (DUT).
The quiescent power supply current IDDQ may include a leakage current flowing even in a defect-free (indefectible) device called “an intrinsic leakage current” or “a normal leakage current”) and a defect current occurring due to a defect in the DUT. That is, the quiescent power supply current IDDQ is defined as the total of the normal leakage current and the defect current.
The normal leakage current can be expressed by the total of the leakage current (FET leakage current) generated from the structure of the metal oxide semiconductor field effect: transistors (MOSFETs) and the leakage current (circuit leakage current) occurring due to circuit operation. The circuit leakage current may be generated by analog circuits, pull-up circuits, bus collision, etc.
In an IDDQ test measuring the quiescent power supply current of a CMOS integrated circuit (IC) device and determining an IC device to be defective when the measured value is more than a threshold value, as described in T. W. Williams, R. H. Dennard, and R. Kapur, “Iddq Test: Sensitivity Analysis of Scaling”, in Int. Test Conf., pp. 786-792, IEEE, 1996, accurate determination is sometimes difficult. The reason is, for example, when the interconnection patterns in an CMOS integrated circuit are extremely fine, the leakage current of the MOSFETs (FET leakage current) increases exponentially along with the fineness. Therefore, various methods have been proposed to reduce the FET leakage current during an IDDQ test.
As a method for reducing the FET leakage current during an IDDQ test, there is known the method of lowering the threshold value by lowering the FET leakage current when strobing. As such the method, a low power supply voltage method, low temperature measurement method, and well bias method are known.
Low Power Supply Voltage Method
This method is a reduction method by utilizing the fact that the leakage current falls when the power supply voltage VD is lowered. In this method, however, the lowering of the power supply voltage VD is limited to an extent where no circuit malfunction occurs, so the rate of reduction of the FET leakage current is low. Also, raising or lowering the power supply voltage VD before and after strobing takes several milliseconds (msec), so it takes a long test time, as a result, the cost increases along with this increase in the testing time.
According to A. E. Gattiker and W. Maly, “Toward Understanding ‘Iddq-Only’ Fails”, in Int. Test Conf., pp. 174-183, IEEE, 1998, a failure pass-through current may disappear when the power supply voltage VD is lowered, and the test may not be achieved.
Low Temperature Measurement Method
This method is a reduction method by using the fact that the FET leakage current falls when the operating temperature is lowered.
The lower limit temperature is determined by the guarantee of reliability and the costs of a temperature apparatus system for maintaining a low temperature and the test apparatus, but with consumer use temperature apparatuses for maintaining low temperatures, about 0° C. is the limit, as the rate of reduction of the FET leakage current is low. Further, the expense and running costs of the temperature apparatus are high, so the total test cost rises.
Well Bias Method
The well bias method is described in A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs”, in Int. Test Conf., pp. 146-155, IEEE, 1997.
In this reduction method, wiring for supplying the bias voltage is added, so the chip area of the CMOS integrated circuit increases or the integration may be low.
Further, the rate of reduction of the leakage current in this method is strongly dependent on the variability of the effective gate length Leff, so the FET leakage current may be varied along with miniaturization.
Note that A. Keshavarzi, C. F. Hawkins, K. Roy, and V. De, “Effectiveness of Reverse Body Bias for Low Power CMOS Circuits”, in 8th NASA Symposium on VLSI Design, pp. 2.3.1-2.3.9, October 1999, the rate of reduction is ⅕ when the effective gate length Leff is 0.18 μm, while the rate of reduction is ½ when the effective gate length Leff is 0.13 μm.
As a test method for a CMOS integrated circuit, in addition to test methods using a fixed threshold value, there are known the Delta method and current ratio method.
Delta Method
The Delta method is described in A. C. Miller, “Delta IDDQ Testing”, in U.S. Pat. No. 5,889,408, March 1999. In this method, the test is conducted while providing an upper limit on the difference between the minimum value and maximum value of the IDDQ. Since upper limit values are not set individually for CMOS integrated circuits, the overlooked defect current may be large. Further, a defect current of an extent less than the amount of fluctuation between vector points (measurement points) of the normal leakage current may not be detected.
Current Ratio Method
The current ratio method is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-171529. In this method, the test is conducted while making the ratio of the minimum value and maximum value of the IDDQ a fixed ratio and setting an upper limit, so an overlooked defect current may occur due to the defect current occurring at all vector points. Further, sometimes it is not possible to detect a defect current of an extent less than the amount of fluctuation between vector points of the normal leakage current.
Note, the power supply current of a CMOS integrated circuit can be divided into a transient current at the time of switching and a quiescent current at the time of quiescence. In an IDDQ test, generally the quiescent current at the time of quiescence is measured to determine defective or indefectible (defect-free) of the CMOS integrated circuit.
In the IDDQ tests of the related art, it is assumed that the IDDQ is the leakage current (FET leakage current) in the FETs.
In recent years, it has become important to integrate a plurality of devices of different designs on a single chip in order to reduce the size of portable devices and reduce costs through integration.
Therefore, a need has arisen for IDDQ testing a CMOS integrated circuit with a circuit(s) having a current(s) (circuit leakage current(s)) due to pull-up, pull-down, and bus collision.